HiPAC - key aspects.
At this early stage, we have identified a small number of
aspects which we consider distinguish HiPAC research from
mainstream audio dsp research. Through collaboration and consultation
with interested institutions, individuals and industrial developers, we
hope and expect to refine and probably expand this list.
- the research and development of compute-intensive tools for
audio and music processing
- a focus on the use of massively-parallel and mesh CPU
- the use of "no-compromise" or "ideal" algorithms, rather
than of techniques that may be efficient but at the loss of generality.
- sonic and artistic value takes precedence over issues
of computational load (since we are presuming that that load can be met
by next-generation technology).
Some possible HiPAC programmes:
- rather than implement standard digital wavguides on
Teraflop hardware, develop uncompromised physical models of strings,
plates etc by means of finite difference meshes.
- generate real-time reverb by direct modelling of the
physical space (over the full frequency range of interest), rather than
by means of sampled impulse responses or delay networks.
- investigate the optimum processor architectures for audio
in terms of parallelism, synchronous v threaded computation, latency, and use of
large shared memory spaces. How can we most efficiently combine inherently recursive processes such
as filters with block-based algorithms suited to implementation on massively-parallel hardware?
- what progamming languages do we need to support HiPAC research?
- < your project here!>
HiPAC at Bath
This subject is as new for us as it will be for anyone else. So
far, we have one project to report, and one collaboration.
The Sliding Phase Vocoder and TFM.
This project, funded by the AHRC, ran for a year from September
1 2006. The project aimed to develop the Sliding DFT (SDFT),
where the analysis frame is updated every sample, into a full Phase
Vocoder. Using this we have developed Transformational FM (TFM), pitch
shifting of an input sound where the pitch can be modulated at audio rates, sample
by sample, thus applying the familiar Chowning FM behaviour to an
arbitrary input sound. With the SPV we have found that compared to the standard
phase vocoder (pvoc), latency is reduced by up to 75%. It is of course
much slower than conventional pvoc - but the use of HiPAC-grade
hardware will enable it to run in real time, with tantalising possibilities for interactive live performance.
The results were presented at ICMC 2007 (Copenhagen). The slides from
this presentation, together with some audio examples, are available here.
Collaboration with Clearspeed
Clearspeed manufactures double-precision floating-point accelerator chips (together
with PCI-X and PCI-e cards), widely used to accelerate supercomputer
clusters. A key feature of this hardware is very low power consumption.
Several cards can comfortably be fitted within one host PC.
Each card uses two Clearspeed CSX600 chips, offering computation up to 55Gflops. They
implement a SIMD computational model, with 96 double-precision
Processing Elements (PEs) running in parallel, per chip. The NOS-DREAM studio
currently has four cards, running in pairs under Linux and Windows XP. We are
investigating the use of this hardware to accelerate HiPAC processes
such as the SPV to real-time capability.
For more information please contact us.